The present invention relates to a semiconductor device, and more particularly, to a circuit having a make-link type fuse and a semiconductor device having the same.
A manufactured semiconductor device may include fuses of a break-link type or a make-link type. The break-link type fuse may include a conductive line made of a conductive material such as polysilicon. The break-link type fuse is to be electrically connected when manufactured, and is programmable for an open condition by blowing the conductive line, e.g., using a laser beam. In contrast, the make-link type fuse may include upper and lower conductive layers manufactured with an insulating layer interposed therebetween. The make-link type fuses assumes an open state condition when manufactured, and is programmable for a short circuit condition by electrically connecting the two conductive layers, e.g., using a laser beam.
During programming of a given break-link type fuse, adjacent break-link type fuses might also be affected by the laser beam that may have been used during programming. Therefore, an interval or distance between two adjacent break-link type fuses conventionally, may be kept relatively wide, which in turn may lead to a large layout area.
On the other hand, in the case of a make-link type fuse, the two conductive layers may be electrically connected by a laser beam of an energy that may seem to have a relatively low energy density in comparison to that for programming of break-type fuses. Because of the ability to use a lower energy beam during programming, a distance between the two conductive layers can be made relatively narrow, for enabling layouts with a smaller area in comparison to conventional type break-link embodiments. Make-link type fuses are described in U.S. Pat. No. 4,665,295.
However, since the electrical shorts between the two conductive layers of the make-link type fuses are formed by a laser beam, an electro-migration phenomenon may be effected even if only small currents pass through the fuse. As a result, an electrical link between the two conductive layers may eventually open.
Therefore, even though the make-link type fuse may have a small layout area, it may present a low operation reliability in comparison to the reliability of a break-link type fuse.
FIG. 1 is a circuit diagram illustrating a circuit 10 having a make-link type fuse 12 for use in a conventional semiconductor device. The circuit includes a PMOS transistor 14, a make-link type fuse 12, inverters 14 and 16, and NMOS transistors 18 and 20. Fuse 12 is coupled serially between channels of transistor 14 and the parallel combination of transistors 18, 20.
In operation a control signal CON may be generated by detecting a power-up or may be originated externally. The control signal CON may remain at a “high” level during an initial stage, and may then transition to a logic “low” level when, e.g., a power-up condition is determined, or an automatic pulse is received to trigger the event.
If make-link type fuse F1 has not been programmed for a short condition, it preserves its open state and a node 22 at the drains of NMOS transistors 18, 20 may remain in a floating state.
When the control signal CON having a logic “high” level is applied to the gate 24 of PMOS transistor 14 and gate 26 of NMOS transistor 18, the PMOS transistor 14 is turned-off, and the NMOS transistor 18 is turned-on. A signal having a logic “low” level may then bias node 22. The inverters 15,16 receive the “low” level signal and generate an output signal MS having a logic “low” level. In addition, NMOS transistor 20 is turned-on in response to a logic “high” level provided at node 28 by inverter 15. Inverter 15 and NMOS 20 may serve as a latch to maintain a logic “high” level of the node 28, and to maintain output signal MS with a “low” level via inverter 16.
When the control signal CON transitions from a logic “high” level to a logic “low” level, PMOS transistor 14 is turned-on, and NMOS transistor 18 is turned-off. The output signal MS may maintain a logic “high” level in view of the latch operation of inverter 15 and NMOS transistor 20 and given that the make-link type fuse 12 remains in its open circuit condition.
When the make-link type fuse F1 is programmed to be electrically connected, the drain of PMOS transistor 14 is electrically connected to the drain of NMOS transistor 18 via node 22.
Under these conditions, when the control signal CON assumes a logic “high” level, the PMOS transistor 14 is turned-off, and NMOS transistor 18 is turned-on. Node 22 therefore receives a logic “low” level. Inverters 15, 16 pass a logic low level for signal MS. The NMOS transistor 20 is turned-on by a high level signal of inverter 15. Inverter 15 and NMOS transistor 20 may act together as a latch to maintain node 28 with a high level and node 22 with a low level.
When control signal CON transitions from a logic “high” level to a logic “low” level, PMOS transistor 14 is turned-on, and NMOS transistor 18 is turned-off. Enabled PMOS transistor 14 attempts to charge node 22 with a logic “high” level. The latch operation of inverter 15 and NMOS transistor 20 may keep NMOS transistor 20 turned-on, and thus an electrical current may flow through make-link type fuse 12. This electrical current flowing through the make-link type fuse 12 may cause an electro-migration phenomenon within the fuse, which may result in a previously programmed link of the make-link type fuse 12 being opened.
Consequently, even though the circuit having the conventional make-link type fuse may allow a small layout area, it may suffer a low operation reliability in these applications.
For example, when the break-link type fuse for use in a redundancy circuit of, for example, a semiconductor memory device, is replaced with the make-link type fuse, an electrical current may flow through the make-link type fuse. With such currents, a link of the make-link type fuse may be opened due to the current flow and associated electro-migration.
FIG. 2 is a circuit diagram illustrating a redundancy circuit 30 having a make-link type fuse. The redundancy circuit includes NMOS transistors 34-36, make-link type fuses 38-42, NMOS transistors 44-48, an inverter 50, and OR gate 52.
Gates of NMOS transistors 44-48 receive the signal MS of input terminal 54. The drains of NMOS transistors 44-48 are connected to decoding address input terminals DA1 to DAn, respectively. The sources of the NMOS transistors 44-48 are coupled to respective fuses of the make-link type fuses 38-48. Sources of the NMOS transistors 32-36 are connected to a ground voltage, while the drains thereof are connected to the other side of respective make-link type fuse 38-42. The gates of the NMOS transistors 32-36 receive an inverted version of signal MS via inverter 50. The OR gate 52 generates, e.g., a redundancy address decoding signal PRE at output 56 by ORing signals from the drains of NMOS transistors 32-36.
An example of operation of the redundancy circuit of FIG. 2 is described below in greater detail. For example, it may be assumed that a defect occurs in a memory cell associated with a decoding address of DA1DA2 . . . DAn such as “00 . . . 1”. When a redundancy enable signal MS arrives with (e.g., from a circuit such as that of FIG. 1), a logic “high” level, the redundancy address decoding signal PRE of the memory device may be generated in accordance with the programming of the make-link type fuses 38-42 of FIG. 2.
The particular decoding address DA1DA2 . . . DAn for “00 . . . 1” may be programmed within redundancy circuit 30 by connecting make-link type fuse 42 while keeping the other make-link type fuses in their open condition. Therefore, when a decoding address DA1DA2 . . . DAn of “00 . . . 1” is input, a signal having a logic “high” level may be transferred through the NMOS transistor 48. The OR gate 56 may then generate the redundancy address decoding signal PRE with a logic “high” level.
However, in the redundancy circuit of FIG. 2, in some instances when control signal MS of the control input 54 transitions from a logic “high” level to a logic “low” level, or from a logic “low” level to a logic “high” level, the NMOS transistors 32-36 may be turned-on and a DC current may flow through the link of make-link type fuse 42. Consequently, electro-migration resulting from a current flow through the fuse may cause the link to open. Because of this possibility of the make-link type fuse 42 becoming blown due to electro-migration, stable operation of the circuit cannot be assured.
In addition, drains of the other NMOS transistors, e.g., 32-34 that are connected to the rest of make-link type fuses, e.g., 38-40, except for the make-link type fuse 42, may enter a floating state. And again, stable operation may not be assured.
Therefore, due to the above-described problems, the make-link type fuses conventionally have not been used in such redundancy decoding circuits. Furthermore, because of these difficulties, the make-link type fuses conventionally have not been used in the control signal generating circuit.